Portland-State-University 2024-2025 Bulletin

ECE 481 ASIC: Modeling and Synthesis

Covers the fundamentals of the ASIC design process. The topics include ASIC design Flow, basic HDL constructs, test benches, modeling combinational and synchronous logic, modeling finite state machines, multiple clock domain designs, qualitative design issues, ASIC constructions.

Credits

4

Prerequisite

ECE 371 (with a grade of C or better).
  • Up one level
  • 400