Portland-State-University 2023-2024 Bulletin

ECE 571 Introduction to System Verilog for Design and Verification

Introduction to SystemVerilog: language features to support both design and verification. Good practices for simulation and synthesis, techniques for constructing reusable testbenches. Additional topics may include hardware acceleration and transaction-based verification techniques. Course includes homework and significant final project with presentation. Familiarity with Verilog (such as that attained in ECE 351, ECE 540, ECE 544 or ECE 508: Verilog Workshop) is assumed.


  • Up one level
  • 500