Portland-State-University 2018-2019 Bulletin

ECE 673 Control Unit Design

Synchronous logic, Finite State Machines: and Moore and Mealy models. Design of FSMs from regular expressions, nondeterministic automata, Petri Nets and parallel program schemata. Partitioned control units. Cellular automata. Realization, minimization, assignment and decomposition of FSMs. Partition and decomposition theory and programs. Micro-programmed units. Microprogram optimization. Theory and realization of asynchronous, self-timed and self-synchronized circuits. Project continuation.

Credits

4

Prerequisite

ECE 572/672.
  • Up one level
  • 600