Portland-State-University 2015-2016 Bulletin

ECE 581 ASIC: Modeling and Synthesis

Covers the fundamentals of the ASIC design process. The topics include ASIC design Flow, basic HDL constructs, test benches, modeling combinational and synchronous logic, modeling finite state machines, multiple clock domain designs, qualitative design issues, ASIC constructions. Also offered for undergraduate-level credit as ECE 481 and may be taken only once for credit.

Credits

4

Prerequisite

ECE 371.
  • Up one level
  • 500