Portland-State-University 2014-2015 Bulletin

ECE 481 ASIC: Modeling and Synthesis

Covers the fundamentals of the ASIC design process. The topics include ASIC design Flow, basic HDL constructs, test benches, modeling combinational and synchronous logic, modeling finite state machines, multiple clock domain designs, qualitative design issues, ASIC constructions. Also offered for graduate-level credit as ECE 581 and may be taken only once for credit.




Prerequisites: ECE 371.
  • Up one level
  • 400