Portland-State-University 2014-2015 Bulletin

ECE 571 Introduction to System Verilog for Design and Verification

Introduction to SystemVerilog: language features to support both design and verification. Good practices for simulation and synthesis, techniques for constructing reusable testbenches. Additional topics may include hardware acceleration and transaction-based verification techniques. Course includes homework and significant final project with presentation. Familiarity with Verilog and finite state machines required.

Credits

4

Prerequisite

Prerequisites: ECE 351 or equivalent, or permission of instructor.
  • Up one level
  • 500